．＆㈤㈩㈨Ⅲ㈧Ⅵ＃㈤Ⅵ②
7-2) Timing Characteristics of input signals
Table 7 AC Characteristics (1) ②②②②②②②②②
(VSHA=+5V, VSHD=+3.3V, Ta=25
ㄏ)
Parameter Symbol Min. Typ. Max. Unit Remark
Clock frequency of source driver fCK 4.5
ê
6.8 MHz
Rising time of clock Tcr
ê
ê
20 ns
Falling time of clock Tcf
ê
ê
20 ns DCLK
Pulse width (High level) Tcwh 40
ê
ê
ns
Pulse width (Low level) Tcwl 40
ê
ê
ns
Frequency of start pulse fsp 16.5
ê
28 kHz
Setup time of start pulse Tsusp 15
ê
ê
ns
Hold time of start pulse Thsp 10
ê
ê
ns
Pulse width of start pulse Twsp
ê
ê
1.5/fCK
ns
ǚNote 7-7ǜ
SPL,SPR
Setup time of latch pulse Tsulp 20
ê
ê
ns
Hold time of latch pulse Thlp 20
ê
ê
ns LP
Pulse width of latch pulse Twlp 60
ê
ê
ns
Setup time of PS Tsups 0
ê
ê
杯s
Setup time of PS Tsulps 1
ê
ê
杯s
Hold time of PS Thps 0
ê
ê
杯s
Source
driver
Hold time of PS Thlps 30
ê
ê
ns
PS
Set up time of data Tsud 15
ê
ê
ns
Hold time of data Thd 10
ê
ê
ns
R0эR5,G0эG5
,B0эB5
Clock frequency fcls 16.5
ê
28 kHz
Pulse width of clock(Low) Twlcls 5
ê
(1/fcls)-30
杯s
Pulse width of clock(High) Twhcls 30
ê
ê
杯s
Rising time of clock Trcls
ê
ê
100 ns CLS
Falling time of clock Tfcls
ê
ê
100 ns
Setup time of clock Tsucls 3
ê
ê
杯s
Hold time of clock Thcls 0
ê
ê
杯s
Frequency of start pulse fsps 58
ê
86 Hz
Setup time of start pulse Tsusps 100
ê
ê
ns
Hold time of start pulse Thsps 300
ê
ê
ns
Rising time of start pulse Trsps
ê
ê
100 ns
Gate
driver
Falling
time
of
start pulse Tfsps
ê
ê
100 ns
SPS
Vcom Setup time of Vcom Tsuvcom 0
ê
ê
杯s
Vcom
Hold time of Vcom Thvcom 1
ê
ê
杯s
ǚNote 7-7ǜThere must be only one up-edge of DCLK (includes Tsusp and Thsp time) in the period of
SPL=”Hi”.
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